1. Field of the Invention
The present invention relates to a solid stage imaging device and, more particularly, to a solid state imaging device having a charge expelling part region or an overflow drain region formed adjacently to a horizontal charge transfer part.
2. Description of the Related Art
A solid state imaging device has conventionally been used as a camera-integrated video tape recorder (VTR). As the number of pixels is increased in these years, the solid state imaging device has begun to be used as an input device to an electronic still camera for, in place of film exposure, converting optical information to electric signal and storing the signal in a memory medium to produce hard copy output or to observe it on the screen of a monitor.
In such a solid state imaging device, there exists unnecessary signal charge in a photoelectric converter part or in vertical and horizontal charge transfer parts. When the solid state imaging device is used as an input device to the camera-integrated VTR, since such unnecessary signal charge settles down, after display for a time corresponding to several display screens, to an insignificant level, the unnecessary charge does not present a big problem. When the solid state imaging device is used as an input device to an electronic still camera, however, there exists a time lag after a shutter button is triggered until the shutter is actually opened or closed, thus unfavorably losing the optimum shutter pushing timing.
For this reason, in the case of the solid state imaging device used as the input device to the electronic still camera, unlike it is used to the camera-integrated VTR, it becomes necessary to remove all the unnecessary signal charge present in the photoelectric converter part, vertical and horizontal charge transfer parts simultaneously with the triggering of the shutter button.
One of conventional means for removing such unnecessary charge present in the photoelectric converter part is to use blooming control in which a P.sup.- type semiconductor region having a low concentration is formed directly under an N type semiconductor region forming the photoelectric converter part so that a reverse bias is applied to the N type semiconductor substrate to expel excessive charge to the N type semiconductor substrate; while a vertical overflow drain structure is formed so that the N type semiconductor region per se is depleted to expel all signal charge to the N type semiconductor substrate (refer to a journal of The Institute of Television Engineers of Japan, Vol. 37, No. 10, 1983, pp. 782-787).
Further, with respect to the unnecessary charge present in the horizontal charge transfer part, since the horizontal transfer part can operate at a higher speed, the usual operation enables the unnecessary charge is expelled to a reset drain provided at an end of the horizontal charge transfer part.
Meanwhile, removal of unnecessary charge present in the vertical charge transfer part requires a charge transfer time corresponding to at least one or several display screens.
As a method for removing the unnecessary charge of the vertical charge transfer part, there has been proposed a first method in which a drain for removal of the unnecessary charge is provided at an end of a vertical charge transfer part on the opposite side of a horizontal charge transfer part, a still camera is put in its usable state even when the camera is not in use to previously set an embedded channel of the vertical charge transfer part and a substrate in their reverse biased state to thereby remove the unnecessary charge (Japanese Patent Laid-Open Publication No. 58-31671); a second method in which a drain for removal of unnecessary charge is provided at an end of a vertical charge transfer part CCD opposed to a horizontal charge transfer part to reversely transfer, i.e., remove unnecessary charge on the vertical charge transfer part CCD (Japanese Patent Laid-Open Publication No. 58-31672); or a third method in which a drain is provided in a connection part between horizontal and vertical charge transfer parts and a reset gate is controlled to remove unnecessary charge (Japanese Patent Laid-Open Publication No. 58-31672).
However, these methods have had their defects. That is, the first method has been defective in that, since the vertical charge transfer part is always put in its depleted state, a time taken for removing the unnecessary charge on the vertical charge transfer part becomes very long and a reverse biasing power source must be always applied. The second method has had a disadvantage that the removal of the unnecessary charge is carried out by reversely transferring the unnecessary charge, which undesirably results in that,since the direction of the reverse transfer is different from that of the normal signal charge, this causes local signal loss, leading to a failure thereof (refer to Japanese Laid-Open Publication No. 2-33275). This disadvantage can be undesirably removed only by a complex method for driving the solid state imaging device. Further, the third method requires narrow and fine formation of a control gate and unnecessary charge expelling drain, which makes it difficult to manufacture it. The third method also requires the control gate to be applied with a pulse for controlling it, which leads to the fact that its resultant solid state imaging device must be driven in a complex manner.
To avoid such defects, there has recently been proposed a method in which an unnecessary charge expelling region is formed adjacent to a horizontal charge transfer part so that unnecessary charge of a vertical charge transfer part is removed by forwardly transferring it (refer to Japanese Laid-Open Publication No. 2-205359, No. 62-154881).
FIG. 14 schematically shows an arrangement of a prior art solid state imaging device having an charge expelling part adjacent to a horizontal charge transfer part. The prior art solid state imaging device includes a photoelectric converter part 1101, a vertical charge transfer 1102, a horizontal charge transfer 1103, an output circuit part 1104, an unnecessary charge expelling part 1105, and an N.sup.++ type region 1106 connected to a power supply voltage provided at one end of the unnecessary charge expelling part 1105.
FIG. 15 is a plan view of a region having the unnecessary charge expelling part 1105 adjacent to the horizontal charge transfer 1103 in the prior art, which includes, a vertical charge transfer channel 1201, a horizontal charge transfer channel 1202, a potential barrier region 1203, an unnecessary charge expelling region 1204, a first horizontal charge transfer electrode 1205, a second horizontal charge transfer electrode 1206, and a final vertical charge transfer electrode 1207.
FIG. 16 shows a cross-sectional view of the prior art solid state imaging device of FIGS. 14 and 15 taken along a plane I-I' and a diagram showing its potential. The illustrated cross-sectional view includes an N.sup.-- type semiconductor substrate 1301 having an impurity concentration of about 2.0.times.10.sup.14 cm.sup.-3, a P type well layer 1302 having an impurity concentration of about 1.0.times.10.sup.16 cm.sup.-3, an N type semiconductor region 1303 having an impurity.concentration of about 1.0.times.10.sup.17 cm.sup.-3 and having an embedded or buried channel of vertical and horizontal charge transfer parts and a potential barrier part formed therein, an N.sup.+ type semiconductor region 1305 having an impurity concentration of about 1.0.times.10.sup.18 cm.sup.-3 formed as the unnecessary charge expelling part, a P.sup.+ type semiconductor region 1307 having an impurity concentration of about 1.0.times.10.sup.18 cm.sup.-3 formed as an element separator, a first horizontal charge transfer electrode 1205 made of a first polycrystalline silicon layer 1308, and a final vertical charge transfer electrode 1207 made of a second polycrystalline silicon layer 1309. N type semiconductor region 1303 directly under the vertical charge transfer part, a vertical/horizontal connector part, the potential barrier part is formed to have a width which is narrower than the N type semiconductor region 1303 directly under the horizontal charge transfer part to secure a narrow effect. Applied to the N.sup.+ type semiconductor region 1305 formed as the unnecessary charge expelling part is a power supply voltage V.sub.D of usually about 15V through the N.sup.++ type semiconductor regions 1106 and 1306 provided at one end of the unnecessary charge expelling part and having an impurity concentration of about 1.0.times.10.sup.20 cm.sup.-3 thereby to be in non-depleted state. That is, A whole of the N+ type semiconductor region 1305 exists holes provided from the N++ type semiconductor region 1306. As soon as the unnecessary charge are injected to the unnecessary charge expelling part, the unnecessary charge becomes extinct to recombine with the holes. The horizontal charge transfer part is in depleted stage by its impurity concentration and provided the power supply power. A potential .psi.B at potential barrier part is set up deeper than a potential .PSI.VH at vertical/horizontal connector part so as not to flow backward from the unnecessary charge expelling part to the horizontal charge transfer part.
FIG. 17 shows a cross-sectional view of the prior art solid state imaging device taken along a plane II-II' and also a diagram showing its potential. The illustrated cross-sectional view includes the N.sup.-- type semiconductor substrate 1301, the P type well layer 1302, the N type semiconductor region 1303, an N.sup.++ type semiconductor substrate 1304 having an impurity concentration of about 7.0.times.10.sup.16 cm.sup.-3, an N.sup.++ type semiconductor region 1306,1311 having a floating diffusion layer and a reset drain part formed therein, the P.sup.+ type semiconductor region 1307 formed as an element separator, the first horizontal charge transfer electrode 1205 made of the first polycrystalline silicon layer 1308, and the second horizontal charge transfer electrode 1206 made of the second polycrystalline silicon layer 1309. Applied to the N.sup.++ type semiconductor region forming the reset drain of signal charge is a power supply voltage V.sub.D of usually about 15V.
FIG. 18 shows a cross-sectional view of the prior art solid state imaging device of FIG. 14 taken along a plane III-III' and a diagram showing its potential. The illustrated cross-sectional view includes the N.sup.-- type semiconductor substrate 1301, the P type well layer 1302, the N.sup.+ type semiconductor region 1305 forming the unnecessary charge expelling part, the P.sup.+ type semiconductor region 1307 formed as the element separator, the first horizontal charge transfer electrode 1205 made of the first polycrystalline silicon layer 1308, and the second horizontal charge transfer electrode 1206 made of the second polycrystalline silicon layer 1309. Applied to the N.sup.+ type semiconductor region 1305 is the power supply voltage V.sub.D of usually about 15V through the N.sup.++ type semiconductor region 1306 provided at one end of the unnecessary charge expelling part. The power supply voltage VD applied to N++ type semiconductor region 1306 shown in FIG. 18 is the same voltage source at the power supply voltage VD applied to N++ type semiconductor region 1306 shown in FIG. 17.
Explanation will be made as to the operation of the prior art solid state imaging device having such an arrangement as mentioned above with referring to FIG. 19.
During unnecessary charge expelling duration, as mentioned above, the removal of the unnecessary charge present in the photoelectric converter part 1101 is achieved in such a manner that the P.sup.- type semiconductor region having a low impurity concentration is formed directly below the N type semiconductor region forming the photoelectric converter part and the reverse bias is applied to the N.sup.-- type semiconductor substrate 1301 to deplete the N type semiconductor region itself to thereby expel all signal charge to the N.sup.-- type semiconductor substrate 1301.
Together with the aforementioned operation, the unnecessary charge present in the photoelectric converter part 1101 is transferred all together toward the horizontal charge transfer 1103, e.g., by a 4-phase clock pulse. At this time, applied to the first and second horizontal charge transfer electrodes 1205 and 1206 are a high level voltage V.sub.H at a terminal .phi.H.sub.1 and a low level voltage V.sub.L at a terminal .phi.H.sub.2 as shown in FIG. 16, so that excessive charge, which has been not accumulated in the horizontal charge transfer 1103, is removed or absorbed into the N.sup.+ type semiconductor region 1305 of the unnecessary charge expelling part 1105 provided adjacent to the potential barrier exceeding a potential .PHI.B of the barrier formed deeper than a potential .PHI.VH on a vertical/horizontal connector in such a manner that the excessive charge is prevented from going back to the vertical charge transfer 1102.
With respect to unnecessary charge remained at the horizontal charge transfer 1103, such a 2-phase clock pulse as shown in FIG. 13 causes normal high-speed operation of the horizontal charge transfer part, whereby the remaining charge is removed or absorbed into the N.sup.++ type semiconductor region 1306 of the reset drain provided at one end of the horizontal charge transfer 1103.
Subsequently, the signal charge accumulated in the photoelectric converter part 1101 by the quantity of incident light for a predetermined time is read and sent to the corresponding vertical charge transfer 1102, sent to the horizontal charge transfer 1103 for every horizontal line vertically transferred through the respective vertical charge transfers 1102, horizontally transferred through the horizontal charge transfer 1103, and then output through the output circuit part 1104.
As mentioned above, even if charge signal exceeding an charge transfer ability of the horizontal charge transfer part transfers from the vertical charge transfer part into the horizontal charge transfer part, oversupply charge do not flow back to the vertical charge transfer part. Accordingly, the solid stage imaging device of the prior art can prevent from being white on a monitor display.
However, with such a solid state imaging device having the unnecessary charge expelling region adjacent to the horizontal charge transfer part as mentioned above, the horizontal charge transfer channel 1202, potential barrier region 1203 and unnecessary charge expelling channel 1204 must be formed under the charge transfer electrode 1205 of the horizontal charge transfer part to remove the unnecessary charge overflowing at the horizontal charge transfer part.
For this reason, this solid state imaging device has had a defect that, the number of manufacturing steps is increased to form N type semiconductor region 1303 and N+ type semiconductor region 1305 under the horizontal charge transfer electrode.
Further, since the N.sup.+ type semiconductor region as the unnecessary charge expelling part having a relatively high impurity concentration is formed under the horizontal charge transfer electrode, this solid state imaging device has also had another defect that, upon forming a gate insulating film under the horizontal charge transfer electrode in a later step, outward impurity diffusion from the N.sup.+ type semiconductor region causes formation of an abnormal diffusion layer in the N type semiconductor region as the channel region or the potential barrier region, thus involving variations in the potential.